;********************************************************************** ; This code is copyright James Hardy (2005) * ; You may not use this code for any commercial purpose whatsoever * ; intact or modified without prior permission from the author. * ; You have permission to use this code for personal, non commercial * ; use. You may use or modify the code to your purpose in any * ; way you like, subject to the following conditions: * ; * ; 1. You include this copyright notice in the source code. * ; 2. The code is not used for commercial purposes, without prior * ; permission of James Hardy (the author of this code) * ; 3. You agree that there is no warranty given or implied. * ; 4. You use this software at your own risk. * ; ; In plain English: You can use this software for free, you can * ; modify it if you like but don't try to make money out of the * ; code I have taken the time to develop. * ; Be aware that I can't guarantee anything about this code, it is * ; after all free. * ; * ;********************************************************************** list p=16f627 ; list directive to define processor #include ; processor specific variable definitions ;************************************************************************** ;* (C) J Hardy. RA Drive motor for EQ5/CG5 (4MHz Osc) * ;************************************************************************** W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' CMCON EQU H'001F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01FF' __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'03FF' _CP_75 EQU H'17FF' _CP_50 EQU H'2BFF' _CP_OFF EQU H'3FFF' _DATA_CP_ON EQU H'3EFF' _DATA_CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FEF' _LP_OSC EQU H'3FEC' _XT_OSC EQU H'3FED' _HS_OSC EQU H'3FEE' __CONFIG _BODEN_ON & _CP_OFF & _DATA_CP_OFF & _PWRTE_ON & _WDT_OFF & _LVP_OFF & _MCLRE_OFF & _XT_OSC ; '__CONFIG' directive is used to embed configuration data within .asm file. ; The labels following the directive are located in the respective .inc file. ; See respective data sheet for additional information on configuration word. ;========================================================================== ; Variable Definition ;========================================================================== RA_TIMER1 EQU H'20' ;Used in 'Right Ascension' delay routine RA_TIMER2 EQU H'21' ; " " " RA_TIMER_FINE EQU H'22' ;Used for fine speed control of RA drive rate SW1 EQU H'05' ;SW1 is triggering RA5 SW2 EQU H'04' ;SW2 is triggering RA4 SW3 EQU H'03' ;SW3 is triggering RA3 SW4 EQU H'02' ;SW4 is triggering RA2 SW5 EQU H'01' ;SW5 is triggering RA1 SW6 EQU H'00' ;SW6 is triggering RA0 STEP1 EQU B'00110110' ;Reverse these (STEP1 to STEP4) STEP2 EQU B'00111010' ;for the southern hemisphere STEP3 EQU B'00111001' ;Bit 7: unused, bits 5,4: enable on L293D. Bit 6: indicator LED. STEP4 EQU B'01110101' ;Bits 3,2,1,0: Stepper sequence - inputs to L293D HSTEP1 EQU B'00110110' ;Half Step sequence HSTEP2 EQU B'00101000' ;for the Northern hemisphere HSTEP3 EQU B'00111010' HSTEP4 EQU B'00010001' HSTEP5 EQU B'00111001' HSTEP6 EQU B'00100100' HSTEP7 EQU B'00110101' HSTEP8 EQU B'01010010' ;Blink LED (Bit 6) ;********************************************************************** RESET_VECTOR CODE 0x000 ; processor reset vector goto start ; go to beginning of program MAIN CODE ; ********************************** ; ** RESET : main boot routine ** ; ********************************** start MOVLW B'00000111' ;Disable Comparator module's MOVWF CMCON ; BSF H'0003',H'0005' ;Switch to register bank 1 ;Disable pull-ups ;INT on rising edge ;TMR0 to CLKOUT ;TMR0 Incr low2high trans. ;Prescaler assign to Timer0 ;Prescaler rate is 1:256 MOVLW B'11010111' ;Set PIC options (See datasheet). MOVWF OPTION_REG ;Write the OPTION register. ; CLRF INTCON ;Disable interrupts MOVLW B'10000000' MOVWF TRISB ;RB7 are inputs. (1=input) ;RB6,5,4,3,2,1,0 are outputs. (0=output) MOVLW B'11111111' ;all RA ports are inputs MOVWF TRISA BCF STATUS,RP0 ;Switch Back to reg. Bank 0 CLRF PORTB GOTO RA_Drive ;******************************************************************************************* ; ********************************************* ; * Right Ascension Motor Stepping Routine * ; ********************************************* ; ********************************************* ; * Test for Slew button press * ; ********************************************* RA_Drive BTFSC PORTA,SW6 ;Pressing SW6 stops the RA drive GOTO RA_Drive ;i.e. RA_Drive loops back on itself. BTFSC PORTA,SW1 GOTO RA_Forward BTFSC PORTA,SW2 GOTO RA_Reverse ; ********************************************* ; * Drive at RA Sidereal Rate * ; ********************************************* CALL RA_DELAY MOVLW HSTEP1 MOVWF PORTB CALL RA_DELAY MOVLW HSTEP2 MOVWF PORTB CALL RA_DELAY MOVLW HSTEP3 MOVWF PORTB CALL RA_DELAY MOVLW HSTEP4 MOVWF PORTB CALL RA_DELAY MOVLW HSTEP5 MOVWF PORTB CALL RA_DELAY MOVLW HSTEP6 MOVWF PORTB CALL RA_DELAY MOVLW HSTEP7 MOVWF PORTB CALL RA_DELAY MOVLW HSTEP8 MOVWF PORTB GOTO RA_Drive ; ********************************************* ; * Forward Slew Drive Sequence Sub Routine * ; ********************************************* RA_Forward BTFSC PORTA,SW5 ;Reverse direction switch GOTO RA_Rvs RA_Fwd CALL RA_DELAY_V MOVLW STEP1 MOVWF PORTB CALL RA_DELAY_V MOVLW STEP2 MOVWF PORTB CALL RA_DELAY_V MOVLW STEP3 MOVWF PORTB CALL RA_DELAY_V MOVLW STEP4 MOVWF PORTB GOTO RA_Drive ; ********************************************* ; * Reverse Slew Drive Sequence Sub Routine * ; ********************************************* RA_Reverse BTFSC PORTA,SW5 ;Reverse direction switch GOTO RA_Fwd RA_Rvs CALL RA_DELAY_V MOVLW STEP4 MOVWF PORTB CALL RA_DELAY_V MOVLW STEP3 MOVWF PORTB CALL RA_DELAY_V MOVLW STEP2 MOVWF PORTB CALL RA_DELAY_V MOVLW STEP1 MOVWF PORTB GOTO RA_Drive ; ********************************************* ; * Right Ascension Delay Routine 1 * ; * Timing adjusted for input routine code * ; * execution time * ; ********************************************* ; ********************************************* ; * Right Ascension Delay Slew Routine * ; ********************************************* RA_DELAY_V MOVLW D'25' ;Generate 10x RA delay at 4Mhz CLK (Switch in the middle "OFF" position) BTFSC PORTA,SW4 ;Ignore next instriction if SW4 is off MOVLW D'125' ;Generate 2x RA delay at 4Mhz CLK (Switch in the lower "ON" position) BTFSC PORTA,SW3 ;Ignore next instriction if SW3 is off MOVLW D'10' ;Generate 25x RA delay at 4Mhz CLK (Switch in the upper "ON" position) MOVWF RA_TIMER2 ;For a EQ-5 / CG-5 standard stepper motors RA_LOOP1a MOVLW D'137' ;You may vary this for you drive MOVWF RA_TIMER1 ;250 x 137 = approx 100mS RA_LOOP2a DECFSZ RA_TIMER1,F ;Reverse engineered from a single RA Drive GOTO RA_LOOP2a ;using an oscilloscope. DECFSZ RA_TIMER2,F GOTO RA_LOOP1a RETURN ; ********************************************* ; * RA Delay Routine * ; ********************************************* RA_DELAY MOVLW D'125' ;Generate approx 50mS delay at 4Mhz CLK MOVWF RA_TIMER2 ; put 125 in TIMER2 variable RA_LOOP1b MOVLW D'137' ; MOVWF RA_TIMER1 ; put 137 in TIMER1 variable RA_LOOP2b DECFSZ RA_TIMER1,F GOTO RA_LOOP2b DECFSZ RA_TIMER2,F GOTO RA_LOOP1b MOVLW D'10' ;Fine adjustment delay loop MOVWF RA_TIMER_FINE ; RA_LOOP3b DECFSZ RA_TIMER_FINE,F GOTO RA_LOOP3b RETURN END ; directive 'end of program'